This invention relates in general to the transfer of data between an electronic device and two or more memory or peripheral devices and in particular, where at least one of the memory or peripheral devices requires that its input and output ("I/O") for the data and the data's address be non-multiplexed and on separate leads, and at least one other memory or peripheral device requires that its I/O for the data and the data's address be multiplexed through the same leads.
Many memory or peripheral devices such as EEPROMs, have separate address and data I/O leads and in turn, require separate address and data I/O communication capability from electronic devices to and from which they transmit data. These devices maximize their read/write data access speeds at the expense of increasing their required number of I/O leads.
However, some memory or peripheral devices and especially, certain peripheral devices such as data path controllers, have a single set of I/O leads through which address and data signals are multiplexed and in turn, require electronic devices to and from which they transmit data to also provide a corresponding set of I/O leads through which address and data signals are multiplexed. These devices minimize the number of their required I/O leads at the expense of slowing down their effective read/write data access times.
Frequently, it is desirable for an electronic device such as a microprocesser (".mu.P") to communicate in the same system with memory or peripheral devices of both types. In order to do so, the .mu.P or the .mu.P in conjunction with additional logic external to the .mu.P, must provide address and data signals to both types of devices that are compatible with their different I/O needs.
FIG. 1 illustrates one example of a prior art circuit for accomplishing this. A .mu.P 200 multiplexes and transmits the lower 8-bits of an address, A7-A0, with 8-bits of data, D7-D0, through one set of eight I/O leads 220, and transmits the upper 8-bits of the address, A15-A8, through a separate set of eight I/O leads 210.
An 8-bit address latch 300 receives the multiplexed address/data signals, AD7-AD0, at its I/O leads 230, and latches in only the 8-bit address information, A7-A0, for temporary storage. Storage of only the address information is accomplished by connecting the address strobe signal ("AS") generated by the .mu.P 200 to the latch enable ("LE") of the 8-bit latch 300.
Device 310 is a 32K.times.8 memory device that receives a 15-bit address, A14-A0, and receives or transmits 8 bits of data, D7-D0, through separate I/O leads, 260, 270 and 250 respectively. To interface with the .mu.P 200, the chip enable ("CE") of the memory device 310 is connected to the 16th address bit, A15, from I/O leads 210. The 16th address bit is used for this purpose, because it is otherwise not used when addressing only 32k address locations.
When the .mu.P 200 reads data from the memory device 310, the memory device 310 receives at its I/O leads 260 the lower 8-bits of the data's address from the output leads 240 of the address latch 300, and at its I/O leads 270, the upper 7-bits of the data's address from the first 7 of the set of 8 I/O leads 210. The 8-bit data is then strobed out of the memory device 310 through its I/O leads 250 and to the set of multiplexed address/data I/O leads 220 of .mu.P 200 by the data strobe signal ("DS") which is generated by the .mu.P 200 and connected to the output enable ("OE") of the memory device 310.
Device 320 is a 256.times.8 memory device that requires its 8-bit address, A7-A0, and 8-bit data I/O, D7-D0, to be multiplexed and received/transmitted through the same 8 I/O leads 280. To interface with the .mu.P 200, the chip select ("CS") of the memory device 320 is connected to a data memory control bit ("DM") generated by the .mu.P 200.
The memory device 320 then receives/transmits its multiplexed address/data I/O, AD7-AD0, directly from the I/O leads 220 of the .mu.P 200, which are connected to its I/O leads 280. The 8-bit address and data information are strobed off and on the set of the I/O leads 280 under the control of the AS and DS signals, respectively, which originate from the .mu.P 200 and connect to their respective pin counterparts on the memory device 320.
Although the example of FIG. 1 provides effective communication between the .mu.P 200 and the two external memory devices 310 and 320, in many applications where printed circuit board space is at a premium, the requirement of an additional component such as the 8-bit latch 300 is objectionable. For these applications, an interface configuration that does not require additional interface components is desirable.
Therefore, it is a primary object of the present invention to provide an address/data I/O structure for an electronic device, such as a .mu.P, which can communicate with memory or peripheral devices with address/data I/O structures such as those of devices 310 and 320, respectively, without the necessity of adding additional interface components to the system circuitry.